About Me

I am Khandaker Shams Arefin, an engineer specializing in standard cell layout, memory layout and custom IC layout design. My career began at Ulkasemi Pvt. Ltd., where I contributed to the development of standard cell libraries and memory layouts across technologies such as 12nm FDSOI, 12nm FINFET, 22nm FDSOI, 28nm, 90nm and 130nm. I work on cutting‑edge MRAM, RRAM and MicroLED projects.

My professional expertise spans layout design, from basic standard cells through complex hierarchical blocks and chip‑top floor plans. I have hands‑on experience debugging LVS, DRC, ERC, antenna and IR issues, and am comfortable shielding critical nets and matching devices for optimal performance. In addition to my design work I mentor trainee engineers, providing guidance on best practices and design methodologies.

Outside of work I love exploring the intersection of AI and hardware. I’m currently developing a general‑purpose ANN accelerator for microcontrollers and working on more efficient floating‑point arithmetic units. I hold a Bachelor of Science in Electrical and Electronic Engineering from Ahsanullah University of Science and Technology in Dhaka. I’m now preparing for graduate study and seeking PhD opportunities where I can contribute my hardware design skills and learn from leading researchers.

Professional Experience

• Engineer, Standard Cell & Memory Layout (CSD), Ulkasemi Pvt. Ltd. (Jan 2024 – present) – working on MRAM projects in GlobalFoundries 12LPP.
• Assistant Engineer, Memory Layout (CSD), Ulkasemi Pvt. Ltd. (Nov 2022 – Dec 2023) – delivered a complete standard cell library for GlobalFoundries 90SW‑SOI, including SDFF, DFF, adders and multiplexers.
• Trainee Engineer, CSD, Ulkasemi Pvt. Ltd. (Aug 2022 – Oct 2022) – performed layout compaction for MicroLED projects (22FDXPLUS & 28SLPe) and designed blocks for a WSLM IP including column multiplexers, decoders and drivers.

Professional Expertise

• Extensive layout experience across GF technologies (12LP, 12LPP, 22FDX, 22FDXPLUS, 28FDX, 55BCD, 90SW‑SOI).
• Design and integration from individual standard cells to hierarchical blocks and full chip floor plans.
• Debugging LVS, DRC, ERC, antenna, EM and IR issues; critical net and device shielding.
• Mentoring and training junior engineers.

Education

B.Sc. in Electrical and Electronic Engineering (EEE)
Ahsanullah University of Science and Technology (AUST), Dhaka — Nov 2016 – Jun 2022
CGPA: 2.8/4.0

Technical Skills

• Programming: Python, C++, Verilog HDL, SystemVerilog, MATLAB, HTML5, Skill.
• Layout Design: Cadence Virtuoso Layout Editor.
• Schematic & Simulation: Cadence Virtuoso Schematic Editor, Proteus, LTspice, Pspice, ModelSim, Quartus II.
• Embedded Systems: Arduino, STM32, ESP32, Raspberry Pi Pico, FPGA.

Awards & Leadership

• 2nd place – Educative Tutorial Competition 2020 (BRACU Student Branch).
• Education Board Scholarship recipient.
• General Member and Program Coordinator – IEEE AUST Student Branch.
• Vice President – Government Science College Science Club.
• Team Leader (Solid Engine & Design) – AUST Rocketry.